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1 fn6173.3 isl1532 data sheet dual channel differential dsl line driver the isl1532 is a dual channel differential amplifier designed for driving full rate adsl2+ signals at very low power dissipation. the high drive capability of 450ma makes this driver ideal for dmt designs. it contains two pairs of wideband, high-voltage, curren t mode feedback amplifiers designed on intersil?s hs30 bipolar soi process for low power consumption in dsl systems. these drivers achieve an mtpr distortion measurement of better than 70db, while consuming typically 5ma per dsl channel of total supply current. this supply current can be set using a resistor on the i adj pin. two other pins (c 0 and c 1 ) can also be used to adjust supply current to one of four pre-set modes (full-i s , 3/4-i s , 1/2-i s , and full power-down). c 0 and c 1 inputs are design to pull high initially. floating these inputs will put the device in disable mode. this is contrary to el1528 where c 0 and c 1 inputs pull low initially and is in the enable state when c 0 and c 1 pins are floated. the isl1532 operates on 5v to 15v supplies and retains its bandwidth and linearity over the complete supply range. the device is supplied in a thermally-enhanced 20 ld htssop and the small footprint (4x5mm) 24 ld qfn packages. the isl1532 is specified for operation over the full -40c to +85c temperature range. the isl1532 provides larger output swing at heavy loads, higher slew rate, and higher bandwidth while maintaining pin-to-pin drop-in compatib ility with the el1528. the isl1532 integrates 50k pull-up resistors on c 0 and c 1 pins. features ? 450ma output drive capability ?44.4v p-p differential output drive into 100 ? 5v to 15v supply operation ? mtpr of -70db ? operates down to 2ma per amplifier supply current ? current control pins ? channel separation - 80db @ 500khz ? direct pin-to-pin replacement for el1528 ? pb-free plus anneal available (rohs compliant) applications ? dual port adsl2+ line drivers ? hdsl line drivers pinouts isl1532 (24 ld qfn) top view isl1532 (20 ld htssop) top view 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 vina+ vinb+ gnd iadj nc vinc+ vind+ vina- vinb- voutb voutc vinc- vind- voutd c1ab c0ab vs- nc vouta c1cd c0cd vs+ nc nc thermal pad c0ab c1ab vina+ vinb+ gnd iadj vinc+ vind+ c1cd c0cd vs- vina- voutb vinc- voutd vouta vinb- voutc vind- vs+ 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 thermal pad* *thermal pad internally connected to gnd caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. december 4, 2006
2 fn6173.3 december 4, 2006 ordering information part number (see note) part marking tape & reel package (pb-free) p k g. d w g. # isl1532irz 1532 irz - 24 ld qfn mdp0046 isl1532irz-t7 1532 irz 7? 24 ld qfn mdp0046 isl1532irz-t13 1532 irz 13? 24 ld qfn mdp0046 isl1532ivez 1532 ivez - 20 ld htssop mdp0048 ISL1532IVEZ-T7 1532 ivez 7? 20 ld htssop mdp0048 isl1532ivez-t13 1532 ivez 13? 20 ld htssop mdp0048 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl1532
3 fn6173.3 december 4, 2006 absolute maxi mum ratings (t a = +25c) v s + to v s - supply voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3v to 30v v s + voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 30v v s - voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30v to 0.3v driver v in + voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s - to v s + c 0 , c 1 voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v i adj voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4v esd rating human body model (per mil-std-883 method 3015.7). . . . . . .3kv machine model (per eiaj ed-4701 method c-111) . . . . . . . . .250v current into any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ma output current from driver (static) . . . . . . . . . . . . . . . . . . . . . 50ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/ma x specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a. electrical specifications v s = 12v, r f = 3k , r l = 65 , i adj = c 0 = c 1 = 0v, t a = +25c. amplifiers tested separately. parameter description conditions min typ max unit supply characteristics i s + (full i s ) positive supply current per amplifier all outputs at 0v, c 0 = c 1 = 0v, r adj = 0 3.75 4.9 6.5 ma i s - (full i s ) negative supply current per amplifier all outputs at 0v, c 0 = c 1 = 0v, r adj = 0 -6.3-4.7-3.5 ma i s + (3/4 i s ) positive supply current per amplifier all outputs at 0v, c 0 = 5v, c 1 = 0v, r adj = 0 3.8 ma i s - (3/4 i s ) negative supply current per amplifier all outputs at 0v, c 0 = 5v, c 1 = 0v, r adj = 0 -3.5 ma i s + (1/2 i s ) positive supply current per amplifier all outputs at 0v, c 0 = 0v, c 1 = 5v, r adj = 0 1.87 2.6 3.75 ma i s - (1/2 i s ) negative supply current per amplifier all outputs at 0v, c 0 = 0v, c 1 = 5v, r adj = 0 -3.75 -2.4 -1.75 ma i s + (power-down) positive supply current per amplifier all outputs at 0v, c 0 = c 1 = 5v, r adj = 0 0.25 1.0 ma i s - (power-down) negative supply current per amplifier all outputs at 0v, c 0 = c 1 = 5v, r adj = 0 -1.0 0 ma i gnd gnd supply current per amplifier all outputs at 0v 0.25 ma input characteristics v os input offset voltage -10 1 +10 mv v os v os mismatch -5 0 +5 mv i b + non-inverting input bias current -15 +14 a i b - inverting input bias current -30 +30 a i b -i b - mismatch -25 0 +25 a r ol transimpedance 13.48m e n input noise voltage 3.5 nv/ hz i n -input noise current 2pa/ hz v ih input high voltage c 0 and c 1 inputs, with signal 1.8 v c 0 and c 1 inputs, without signal 1.6 v v il input low voltage c 0 and c 1 inputs 0.8 v i ih0, i ih1 input high current for c 0, c 1 c 0 = 5v, c 1 = 5v 10 20 40 a i il input low current for c 0 or c 1 c 0 = 0v, c 1 = 0v -3.0 -0.3 a isl1532
4 fn6173.3 december 4, 2006 output characteristics v out loaded output swing (r l single-ended to gnd) r l = 100 11.1 v r l = 50 (+) +10.5 +10.95 v r l = 50 (-) -10.95 -10.5 v r l = 25 (+) +10.0 +10.7 v r l = 25 (-) -10.5 -9.6 v i ol linear output current a v = 5, r l = 10 , f = 100khz, thd = -60dbc (10 single-ended) 450 ma i out output current v out = 1v, r l = 1 1a dynamic performance bw -3db bandwidth a v = +5, r l-diff = 100 50 mhz hd2 2nd harmonic distortion f c = 1mhz, r f = 5k , a v = 10, r l-diff = 100 , v out = 2v pp-diff -90 dbc f c = 1mhz, r f = 5k , a v = 10, r l-diff = 50 , v out = 2v pp-diff -85 dbc hd3 3rd harmonic distortion f c = 1mhz, r f = 5k , a v = 10, r l-diff = 100 , v out = 2v pp-diff -80 dbc f c = 1mhz, r f = 5k , a v = 10, r l-diff = 50 , v out = 2v pp-diff -65 dbc mtpr multi-tone power ratio 26khz to 1.1mhz, r line = 100 , p line = 20.4dbm -70 dbc sr slew rate (single-ended) v out from -8v to +8v measured at 4v 200 400 v/s electrical specifications v s = 12v, r f = 3k , r l = 65 , i adj = c 0 = c 1 = 0v, t a = +25c. amplifiers tested separately. (continued) parameter description conditions min typ max unit pin descriptions 20 ld htssop 24 ld qfn pin name function circuit 1 23 c0ab (note 1) dsl channel 1 current control pin circuit 1 2 24 c1ab (note 1) dsl channel 1 current control pin (reference circuit 1) 5, 11, 12, 21 nc not connected 3 1 vina+ amplifier a non-inverting input circuit 2 4 2 vinb+ amplifier b non-inverting input (reference circuit 2) v s + i adj 20k c oab v s + v s - 50k 2.6v v s + v s - 7.5k isl1532
5 fn6173.3 december 4, 2006 6 4 iadj (note 2) supply current control pin for both dsl channels 1 and 2 circuit 3 5 3 gnd ground connection 7 6 vinc+ amplifier c non-inverting input (reference circuit 2) 8 7 vind+ amplifier d non-inverting input (reference circuit 2) 9 8 c1cd (note 3) dsl channel 2 current control pin (reference circuit 1) 10 9 c0cd (note 3) dsl channel 2 current control pin (reference circuit 1) 11 10 vs+ positive supply 12 13 voutd amplifier d output (reference circuit 2) 13 14 vind- amplifier d inverting input (reference circuit 2) 14 15 vinc- amplifier c inverting input (reference circuit 2) 15 16 voutc amplifier c output (reference circuit 2) 16 17 voutb amplifier b output (reference circuit 2) 17 18 vinb- amplifier b inverting input (reference circuit 2) 18 19 vina- amplifier a inverting input (reference circuit 2) 19 20 vouta amplifier a output (reference circuit 2) 20 22 vs- negative supply notes: 1. amplifiers a and b comprise dsl channel 1. c 0ab and c 1ab control i s settings for dsl channel 1. 2. i adj controls bias current (i s ) setting for both dsl channels. 3. amplifiers c and d comprise dsl channel 2. c 0cd and c 1cd control i s settings for dsl channel 2. pin descriptions 20 ld htssop 24 ld qfn pin name function circuit v s + gnd i adj v s - typical performance curves figure 1. differential frequency response vs r f (full i s ) figure 2. differential frequency response vs r f (3/4 i s ) a v = 10 v s = 12v r l = 100 r adj = 0 r f = 4k r f = 3k r f = 2k r adj = 0 r f = 4k r f = 3k r f = 2k isl1532
6 fn6173.3 december 4, 2006 figure 3. differential frequency response vs r f (1/2 i s ) figure 4. common-mode frequency response vs r f (full i s ) figure 5. common-mode frequency response vs r f (3/4 i s ) figure 6. common-mode frequency response vs r f (1/2 i s ) figure 7. differential frequency response vs r f (full i s ) figure 8. differential frequency response vs r f (3/4 i s ) typical performance curves (continued) r f = 4k r f = 3k r f = 2k a v = 10 v s = 12v r l = 100 r adj = 0 r f = 3k a v = 10 v s = 12v r l = 100 a v = 1 common-mode r f = 2k r f = 3k a v = 10 v s = 12v r l = 100 a v = 1 common-mode r f = 2k r f = 3k a v = 10 v s = 12v r l = 100 a v = 1 common-mode r f = 2k r adj = 0 r f = 3k r f = 2k r f = 4k r adj = 0 r f = 2k r f = 4k r f = 3k isl1532
7 fn6173.3 december 4, 2006 figure 9. differential frequency response vs r f (1/2 i s ) figure 10. common-mode frequency response vs r f (full i s ) figure 11. common-modefrequency response vs r f (3/4 i s ) figure 12. common-mode frequency response vs r f (1/2 i s ) figure 13. differential frequency response vs c l (full i s ) figure 14. differential frequency response vs c l (3/4 i s ) typical performance curves (continued) a v = 5 v s = 12v r l = 100 r adj = 0 r f = 2k r f = 4k r f = 3k r f = 3k a v = 5 v s = 12v r l = 100 a v = 1 common_mode r f = 2k r f = 2k a v = 5 v s = 12v r l = 100 a v = 1 common-mode r f = 3k r f = 3k r f = 2k a v = 5 v s = 12v r l = 100 a v = 1 common-mode a v = 5 v s = 12v r l = 100 r f = 3k 47pf 27pf 0pf 15pf a v = 5 v s = 12v r l = 100 r f = 3k 47pf 0pf 27pf 15pf isl1532
8 fn6173.3 december 4, 2006 figure 15. differential frequency response vs c l (1/2 i s ) figure 16. differential frequency response vs c l (full i s ) figure 17. differential frequency response vs c l (3/4 i s ) figure 18. differential frequency response vs c l (1/2 i s ) figure 19. differential frequency response vs r l (full i s ) figure 20. differential frequency response vs r l (3/4 i s ) typical performance curves (continued) a v = 5 v s = 12v r l = 100 r f = 3k 47pf 27pf 0pf 15pf 47pf 0pf 27pf a v = 10 v s = 12v r l = 100 r f = 3k 15pf 47pf 0pf 27pf a v = 10 v s = 12v r l = 100 r f = 3k 15pf 0pf 27pf a v = 10 v s = 12v r l = 100 r f = 3k 15pf 47pf v s = 12v r f = 3k a v = 10 r l = 220 r l = 365 r l = 475 r l = 100 a v = 10 r l = 100 r l = 365 r l = 475 r l = 220 isl1532
9 fn6173.3 december 4, 2006 figure 21. differential frequency response vs r l (1/2 i s ) figure 22. differential frequency response vs r l (full i s ) figure 23. differential frequency response vs r l (3/4 i s ) figure 24. differential frequency response vs r l (1/2 i s ) figure 25. harmonics distortion vs differential output voltage (full i s ) figure 26. harmonics distortion vs differential output voltage (3/4 i s ) typical performance curves (continued) v s = 12v r f = 3k a v = 10 r l = 220 r l = 365 r l = 475 r l = 100 a v = 5 r l = 220 r l = 365 r l = 475 r l = 100 a v = 5 r l = 100 r l = 365 r l = 475 r l = 220 a v = 5 r l = 100 r l = 365 r l = 475 r l = 220 r f = 3k hd3 thd differential v op-p thd v s = 12v freq = 1mhz a v = 5 r l = 100 r f = 3k hd2 hd3 differential v op-p isl1532
10 fn6173.3 december 4, 2006 figure 27. harmonics distortion vs differential output voltage (1/2 i s ) figure 28. harmonic distortion vs differential output voltage (full i s ) figure 29. harmonic distortion vs differential output voltage (3/4 i s ) figure 30. harmonic distortion vs differential output voltage (1/2 i s ) figure 31. harmonic distortion vs differential output voltage (full i s ) figure 32. harmonic distortion vs differential output voltage (3/4 i s ) typical performance curves (continued) hd2 v s = 12v freq = 1mhz a v = 5 r l = 100 r f = 3k hd3 thd differential v op-p v s = 6v freq = 1mhz a v = 5 r l = 100 r f = 3k thd hd2 hd3 differential v op-p v s = 6v freq = 1mhz a v = 5 r l = 100 r f = 3k hd3 hd2 thd differential v op-p v s = 6v freq = 1mhz a v = 5 r l = 100 r f = 3k thd hd2 hd3 differential v op-p v s = 12v freq = 200khz a v = 5 r l = 100 r f = 3k thd hd2 hd3 differential v op-p thd hd3 hd2 v s = 12v freq = 200khz a v = 5 r l = 100 r f = 3k differential v op-p isl1532
11 fn6173.3 december 4, 2006 figure 33. harmonic distortion vs differential output voltage (1/2 i s ) figure 34. supply current vs supply voltage figure 35. quiescent supply current vs r adj figure 36. output impedance vs frequency figure 37. channel separation vs frequency figure 38. psrr vs frequency typical performance curves (continued) v s = 12v freq = 200khz a v = 5 r l = 100 r f = 3k thd hd3 hd2 differential v op-p 1/2 power mode 3/4 power mode full power mode v) 6 vdc 12 vdc r adj ( ) 100 1 0.01 100m r out ( ) 1k frequency (hz) 10 0.1 100k 10m 10k 1m ab <==> cd psrr- psrr+ isl1532
12 fn6173.3 december 4, 2006 figure 39. differential gain/phase (full i s ) figure 40. differential gain/phase (3/4 i s ) figure 41. differential gain/phase (1/2 i s ) figure 42. voltage and current noise vs frequency figure 43. package power dissipation vs ambient temperature figure 44. package power dissipation vs ambient temperature typical performance curves (continued) v s = 12v a v = 2 r f = 3k r set = 0 phase gain relative gain and phase r l = 100 r set = 0 relative gain and phase r l = 100 r set = 0 phase gain relative gain and phase r l = 100 ja =35c/w jedec jesd51-7 high effective thermal conductivity test board - qfn and htssop exposed diepad soldered to pcb per jesd51-5 qfn24 ja =37c/w 3.571w jedec jesd51-3 low effective thermal conductivity test board 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 893mw htssop20 ja =125c/w qfn24 ja =140c/w 1.000w isl1532
13 fn6173.3 december 4, 2006 applications information the isl1532 consists of two sets of high-power line driver amplifiers that can be connect ed for full duplex differential line transmission. the amplifiers are designed to be used with signals up to 10mhz and produce low distortion levels. the isl1532 has been optimized as a line driver for adsl2+ co application. the driver output stage has been sized to provide full adsl2+ co power level of 20dbm onto the telephone lines. realizing that the actual peak output voltages and currents vary with the line transformer turns ratio, the isl1532 is designed to support 450ma of output current which exceeds the level required for 1:2 transformer ratio. a typical adsl2+ interface circuit is shown in figure 45. each amplifier has identical positive gain connections, and optimum common-mode rejection occurs. further, dc input errors are duplicated and create common-mode rather than differential line errors. input connections the isl1532 amplifiers are somewhat sensitive to source impedance. in particular, they do not like being driven by inductive sources. more than 100nh of source impedance can cause ringing or even oscillations. this inductance is equivalent to about 4? of unshielded wiring, or 6? of unterminated transmission line. normal high-frequency construction obviates any such problem. power control function the isl1532 contains two forms of power control operation. two digital inputs, c 0 and c 1 , can be used to control the supply current of the isl1532 drive amplifiers. c 0 and c 1 inputs are designed to pull high initially. floating these inputs will put the device in disable mode. as the supply current is redu ced, the isl1532 will start to exhibit slightly higher levels of distortion and the frequency response will be limited. t he four power modes of the isl1532 are set up as shown in table 1. another method for controlling the power consumption of the isl1532 is to connect a resistor from the i adj pin to ground. when the i adj pin is grounded (the normal state), the supply current per channel is as per the electrical specifications table on page 3. when a resistor is inserted, the supply current is scaled according to the ?r set vs i s ? graphs in the performance curves section. both methods of power control can be used simultaneously. in this case, positive and negative supply currents (per amp) are given by the equations below: power supplies and dissipation due to the high power drive capability of the isl1532, much attention needs to be paid to power dissipation. the power that needs to be dissipated in the isl1532 has two main contributors. the first is the quiescent current dissipation. the second is the dissipation of the output stage. the quiescent power in the isl1532 is not constant with varying outputs. in reality, 50 % of the total quiescent supply current needed to power each driver is converted in to output current. therefore, in the equat ion below we should subtract the average output current, i o , or 1/2 i q , whichever is the lowest. we?ll call this term i x . where: ?v s is the supply voltage (v s + to v s -) ?i s is the operating supply current (i s + - i s -) / 2 ?i x is the lesser of i o or 1/2 i q the dissipation in the output stage has two main contributors. firstly, we have the average voltage drop across the output transistor and secondly, the average output current. for minimal power dissipation, the user should select the supply voltage and the line transformer ratio accordingly. the supply voltage should be kept as low as possible, while the transformer ratio should be selected so that the peak voltage required from the isl1532 is cl ose to the maximum available - + - + - + - + receive out - receive out + driver input + 2r g r f r f r f r r in r r in r f r out r out line + line - receive amplifiers r line driver input - figure 45. typical line interface connection table 1. power modes of the isl1532 c 1 c 0 operation 00i s full power mode 0 1 3/4 i s power mode 1 0 1/2 i s power mode 1 1 power-down i s +0.34ma 5.06ma 1r set / 1300 () + ------------------------------------------------ - x 3/4c 1 1/2c 0 - c 1 c 0 1/4 + () + = (eq. 1) i s - -5.06ma 1r set / 1300 () + ------------------------------------------------ - x 3/4c 1 1/2c 0 - c 1 c 0 1/4 + () = p dquiescent v s i s ( - 2i x ) = (eq. 2) isl1532
14 fn6173.3 december 4, 2006 output swing. there is a trade off, however, with the selection of transformer ratio. as the ratio is increased, the receive signal available to the receivers is reduced. once the user has selected the transformer ratio, the dissipation in the output stages can be selected with the following equation: where: ?v s is the supply voltage (v s + to v s -) ?v o is the average output voltage per channel ?i o is the average output current per channel the overall power dissipation (p diss ) is obtained by summing p dquiescent and p dtransistor . estimating line driver power dissipation in adsl2+ co applications figure 46 shows a typical adsl co line driver implementation. the average li ne power requirement for the adsl2+ co application is 20dbm (100mw) into a 100 line which translated to 3.16v rms line voltage. the adsl2+ dmt peak to average ratio (crest factor) of 5.3 implies peak voltage of 16.7v into the line. using a differential drive configuration and transformer coupling with standard back termination, a transformer ratio of 1:1 is selected. with 1:1 transformer ratio, the impedance across the driver side of the transformer is 100 , the average voltage is 3.16v rma and the average current is 31.6ma. the power dissipated in the isl1532 is a combination of the quiescent power and the output stage power when driving the line: in the full power mode and with 1.5k r adj resistor, the isl1532 consumes typically 2.7ma quiescent current per amplifier and still able to maintain very low distortion. the distortion results are shown in typical performance section of the data sheet. when driving a load, a large portion (about 50%) of the quiescent current becomes output load current. the total power dissipation per channel is: where: the total power dissipation for dual channel is: p dtotal = 2 x p d = 1247mw the ja requirement needs to be calculated. this is done using the equation: where: ?t junct is the maximum die temperature (+150c) ?t amb is the maximum ambient temperature (+85c) ?p diss is the dissipation calculated above ? ja is the junction to ambient thermal resistance for the package when mounted on the pcb pcb layout considerations for qfn and htssop packages the isl1532 die is packaged in two thermally-efficient packages: a 24 ld qfn (leadless plastic) and 20 ld htssop packages. both have the thermal pads underneath the package and can use pcb surface metal vias areas and internal ground planes to spread heat away from the package. the larger the pcb area, the lower the junction temperature of the device will be. in adsl applications, multiple layer circuit boards with internal ground plane are generally used. 13 mil vias are recommended to connect the metal area under the device with the internal ground plane. examples of the pcb layouts for the qfn and htssop packages are shown in figures 47 and 48 respectively. 37c/w (qfn package) and +35c/w (htssop package) are obtained with the isl153 2 demoboard. the demoboard is a 4-layer board built with 2 oz. copper and has a dimension of 4 in 2 . a separate application note for the qfn package and layout recommendation is available. if using the qfn package, the layout and manufacturing process recommendations should be carefully reviewed. p dtransistors 2i o v s 2 ------- - v o ?? ?? = (eq. 3) p d p quiescent p output-stage + = p d v s i s ( - 2i x ) v s ( - 2 v out-rms ) i out-rms + = (eq. 4) p d 24 2.7ma ( 250% ) 2 31.6ma + 12 ( - 3.16 ) = (eq. 5) p d 623mw = ja t junct - t amb p diss -------------------------------------------- - = (eq. 6) ja 150 - 85 1247mw ------------------------ 52 c/w = = (eq. 7) - + - + txfr 1:1 50 50 r f r f 1.5k 100 r t r t v s - v s + v s - v s + 3k 3k 2r g t x + t x - from afe 0.22f 0.22f figure 46. typical adsl co line driver implementation isl1532
15 fn6173.3 december 4, 2006 output loading while the drive amplifiers c an output in excess of 500ma transiently, the internal metallization is not designed to carry more than 100ma of steady dc current and there is no current-limit mechanism. the device can safely drive rms sinusoidal currents of 2 x 100ma, or 200ma. this current is more than that required to drive line impedances to large output levels, but output short circuits cannot be tolerated. the series output resistor will usually limit currents to safe values in the event of line shorts. driving lines with no series resistor is a serious hazard. the amplifiers are sensitive to capacitive loading. more than 25pf will cause peaking of the frequency response. the same is true of badly termin ated lines connected without a series matchi ng resistor. power supplies and component placement the power supplies should be well bypassed close to the isl1532. a 2.2f tantalum capacitor and a 0.1f ceramic capacitor for each supply works well. since the load currents are differential, they should not travel through the board copper and set up ground loops that can return to amplifier inputs. due to the class ab output stage design, these currents have heavy harmonic content. if the ground terminal of the positive and negative bypass capacitors are connected to each other directly and then returned to circuit ground, no such ground loops will occur. this scheme is employed in the layout of the isl1532 demonstration board, and documentation can be obtained from the factory. the parallel combination of the feedback resistor and gain setting resistor and parasitic capacitance on the inverting input node forms a pole in the feedback path. if the frequency of this pole is low, it can lead to frequency peaking. since the isl1532 is a current feedback amplifier, the feedback resistor value is predetermined by design. the only way to increase the frequency of this pole is to reduce the parasitic capacitance on the inverting input node. ground plane near the inverting input should be avoided to minimize the parasitic capacitance. single supply operation the isl1532 can also be powered from a single supply voltage. when operating in this mode, the gnd pins can still be connected directly to gnd and the c 0 and c 1 pins are relative to gnd. to calculate power dissipation, the equations in the previous section should be used, with v s equal to half the supply rail. feedback resistor value the bandwidth and peaking of the amplifiers varies with supply voltage somewhat a nd with gain settings. the feedback resistor values can be adjusted to produce an optimal frequency response. here is a series of resistor values that produce an optimal driver frequency response (1db peaking) for different supply voltages and gains: top metal internal ground plane figure 47. pcb layout - qfn package top metal internal ground plane figure 48. pcb layout - htssop package isl1532
16 fn6173.3 december 4, 2006 the isl1532 features improved frequency compensation for all power modes and applications, allowing stable operation at very low power levels and eliminating any need for external "snubber" circuits. differential circuits, such as adsl2+ line driver applications, can be especially prone to common-mode oscillation. the isl1532 is specifically compensated to eliminate this type of instability and allow for reliable operation even at very low power levels. cable termination techniques the traditional circuit for a line driver with passive termination is shown in figure 49. r bm is the backmatch resistance added for proper termi nation at the source. this backmatch resistance is typically equal to the value of the cable line characteristic imped ance and the load impedance. the output impedance of the am plifier is negligible in comparison with the value of the backmatch resistor it appears in series with. the gain equation reflects the output voltage across the load resistance with respect to the input voltage. while functional, this passive termination circuit has some disadvantages. the output imped ance of the driver, while small, can be a noticeable quant ity. the backmatch resistor is necessary to properly terminate the source end of a transmission line such as a twisted pair, but now the voltage delivered to the load is split between that backmatch resistance and the load resistance. since there is a required voltage level at the load, the driver must now produce twice the voltage swing. the voltage swing and power dissipation increases. the power burned in the backmatch resistor is lost as heat which causes the total power dissipation to doubled. there also is quiescent power used in the op amp. an alternative technique of cable termination using positive feedback is shown in figure 50. with negative feedback already in place to set the gain, positive feedback can be used to adjust the output impedance. lowering the backmatch resistor without compromising the total source termination impedance relaxes the output and supply voltage requirement for the amplifier and reduces the overall power dissipation. r p1 and r p2 are the only additions to the passive circuit and provide th e positive feedback for the amplifier. this feedback synthesizes larger output impedance for the amplifier, allowing a reduction of the backmatch resistance. for conv enience, a factor k is being introduced. it is the ratio between the backmatch resistance and the physical backmatch resistor. the stability of the amplifier and the physical backmatch resistance tolerance typically limit k to around 4 or 5. the output impedance of the amplifier is increased by the positive feedback, allowing the backmatch resistance to decrease-keeping the total source impedance constant. figure 51 shows a standard method for measuring the output impedance of any circuit. ohm's law applies, so a measured voltage (v x ) applied to a node divided by the test current gives the impedance seen at that node. ideal op amp simplifications (input terminals are at the same voltage and there is no current flowing into the inputs) r p2 is assumed much larger the r bm so the current through the positive feedback loop can be neglected. the voltage at the input terminals is given by a resistive divider of the output voltage on either side of the backmatch resistor. these feedback resistors alter the output resistance for the op amp, allowing reduction in the backmatch re sistance. the de rivations are as follows: table 2. optimum driver feedback resistor for various gains and supply voltages supply voltage driver voltage gain 510 12v 4k 3k - + r f r g v in r bm z l r l v o v o v in --------- 1 r f r g -------- + ?? ?? ?? r l r bm r l + -------------------------- ?? ?? ?? = figure 49. traditional cable termination technique k r l rbm ------------- - = (eq. 8) - + r f r g v in r bm z l r l v o r p2 r p1 figure 50. active termination technique - + r f r g r bm v x r p2 r p1 i x figure 51. measuring output impedance isl1532
17 fn6173.3 december 4, 2006 the overall gain of the active termination circuit is: in an adsl2+ system, the pots phone line, a twisted pair cable is used for data transmission. as shown in figure 52, the single ended active terminate line driver is reconfigured to drive differential lines. the ga in resistor is shared to allow accurate gain matching between the two amplifiers. applying the same analysis technique as the single ended circuit, the following relationship can be derived: table 3 is a quick comparison of the reduction in voltage and power requirements for the driver with passive or active termination. the key specification of a adsl2+ co driver are as follows: peak output line power is 20dbm, pots line impedance is 100 and the crest factor for adsl dmt signal is 14.5db. this specif ication translates to 16.76v peak-to-peak voltage on the line with 5.3 peak to average ratio par and 31.6ma average output current. in the passive termination case where the load and backmatch resistors are the same, the amplifier must provide 33.52v peak-to-peak at its outputs. a high voltage line driver typically needs 4v of total headroom. as a result the total supply voltage required is 37.5v . with the necessary output average current, that translat es into 1.185w dissipated in addition to the quiescent power of the amplifier. in the active case, a k of 5 is assumed. this reduces the backmatch resistor to 20% of its value in the passive case. the peak-to-peak output voltage pr ovided by the driver is reduced to 20.11v which allows the use of the el1508, a median voltage line driver. the el1508 requires 2.5v of headroom. with 2.5v of supply voltage headroom, the power supply required becomes 22.61. with the same output current drive, the power dissip ation is reduced by 39.7% to 0.714w. while it is true that additional power is dissipated in the feedback networks, the feedback resistors are typically much larger than the backmatch resistor and their losses are negligible. v+ r p1 r p1 r p2 + ---------------------------- - v x = v- r g r f r g + ---------------------- v o = r source v x i x ------- r bm / 1 - r p1 r p1 r p2 + ---------------------------- - r f r g + r g ---------------------- ?? ?? ?? == r source r l krbm == k11 - r p1 r p1 r p2 + ---------------------------- - ?? ?? ?? r f r g + r g ---------------------- ?? ?? ?? ? = (eq. 9) v o v in --------- ?? ?? ?? r p2 / r p2 r p1 + () 1 1 k --- - + ?? ?? / r g r f + r g ---------------------- ?? ?? ?? - r p1 r p2 r p1 + ---------------------------- - ?? ?? ?? ---------------------------------------------------------------------------------------------- - = (eq. 10) - + r f r g - + r f r g v in - v in + r p r p v o - v o + r bm r bm r l figure 52. differential line driver using active termination technique k 1 / 1 - r f r p ------- - ?? ?? ?? = v out v in --------------- - ?? ?? ?? 1r f / r g r f / r p + + 21 - r f r p ------- - ?? ?? ?? ----------------------------------------------------------- - = (eq. 11) table 3. passive termination active termination 16.5v p-p into a 100 line 16.5v p-p into a 100 line v out driver = v rbm + v rload v out driver = v rbm + v rload rbm = r load rbm = r load /5 v rbm = v rload v rbm = v rload /5 v out driver = 33.52v v out driver = 20.11v v supply = 37.52 v supply = 24.11 i out = 31.6ma i out = 31.6ma p out driver = v supply * i out = 1.185w (plus quiescent power) p out driver = v supply * i out = 0.714w (plus quiescent power) isl1532
18 fn6173.3 december 4, 2006 isl1532 qfn (quad flat no-lead) package family pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c mdp0046 qfn (quad flat no-lead) package family (compliant to jedec mo-220) symbol qfn44 qfn38 qfn32 tolerance notes a 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 0.02 - c 0.20 0.20 0.20 0.20 reference - d 7.00 5.00 8.00 5.00 basic - d2 5.10 3.80 5.80 3.60/2.48 reference 8 e 7.00 7.00 8.00 6.00 basic - e2 5.10 5.80 5.80 4.60/3.40 reference 8 e 0.50 0.50 0.80 0.50 basic - l 0.55 0.40 0.53 0.50 0.05 - n 44 38 32 32 reference 4 nd 11 7 8 7 reference 6 ne 11 12 8 9 reference 5 symbol qfn28 qfn24 qfn20 qfn16 toler- ance notes a 0.90 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 0.02 - c 0.20 0.20 0.20 0.20 0.20 reference - d 4.00 4.00 5.00 4.00 4.00 basic - d2 2.65 2.80 3.70 2.70 2.40 reference - e 5.00 5.00 5.00 4.00 4.00 basic - e2 3.65 3.80 3.70 2.70 2.40 reference - e 0.50 0.50 0.65 0.50 0.65 basic - l 0.40 0.40 0.40 0.40 0.60 0.05 - n 28 24 20 20 16 reference 4 nd 6 5 5 5 4 reference 6 ne 8 7 5 5 4 reference 5 rev 10 12/04 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminal s on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be squar e or circular in shape with radius (b/2) as shown. 8. if two values are listed, multiple exposed pad options are available. refer to device-specific datasheet.
19 fn6173.3 december 4, 2006 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html isl1532 htssop (heat-sink tssop) family n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane bottom view exposed thermal pad e2 d1 mdp0048 htssop (heat-sink tssop) family symbol 14 ld 20 ld 24 ld 28 ld 38 ld toler- ance a 1.20 1.20 1.20 1.20 1.20 max a1 0.075 0.075 0.075 0.075 0.075 0.075 a2 0.90 0.90 0.90 0.90 0.90 +0.15/-0.10 b 0.25 0.25 0.25 0.25 0.22 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 6.50 7.80 9.70 9.70 0.10 d1 3.2 4.2 4.3 5.0 7.25 reference e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e2 3.0 3.0 3.0 3.0 3.0 reference e 0.65 0.65 0.65 0.65 0.50 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference n 1420242838 reference rev. 2 12/03 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. inter- lead flash and protrusions sh all not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tole rancing per asme y14.5m - 1994.

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